`timescale 1ns/100ps
module TB_uPMips;
  
reg Clk, Reset;
reg [31:0] PortIn;

initial begin
   Clk = 1'b0;
   forever #5 Clk = ~Clk;
end

initial begin
  Reset = 1'b0;
  PortIn = 32'h 00_00_00_04;
    #3  Reset = ~Reset;
    #10  Reset = ~Reset;
  #70 PortIn = 32'h 00_00_00_06;
  #60 PortIn = 32'h 00_00_00_05;    
  #120 PortIn = 32'h 00_00_00_01;    
  #140 PortIn = 32'h 00_00_00_03;
  #200 PortIn = 32'h 00_00_00_69;
end
uPMips uMips(.Clk(Clk),.Reset(Reset),.PortIn(InPort));

endmodule